STMicroelectronics STA8610A TeseoVI+ Quad-Band GNSS Receivers

STMicroelectronics STA8610A Automotive TeseoVI+ Quad-Band GNSS Receivers feature dual independent Arm^® Cortex^®-M7 processing cores for local control of all integrated circuit (IC) functions. These quad-band multi-constellation positioning receiver ICs support multiband constellations up to quad-band with a single-die approach, while the dual-processor architecture provides enough resources to support the RTK/PPP precision algorithms on the chip. The STA8610A series offers an ideal open platform for augmenting with high-value software features and supports anti-spoofing and precise heading algorithms. This STMicroelectronics series includes a hardware security module (HSM) to support secure boot and is an ideal solution for applications where integrity is vital. The STA8610A receivers support emerging low Earth orbit (LEO) constellations and comply with ST automotive-grade qualification and AEC-Q100 requirements.

Features

AEC-Q100 automotive qualification ongoing
ESD: 2kV (HBM) and 500V (CDM)
Automotive grade +105°C
GNSS
- STMicroelectronics' 6th Gen positioning receiver with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, and NAVIC (former IRNSS)
- Open platform supported by software development kit (SDK)
- Standard PVT positioning supporting up to quad-band for submeter accuracy applications
- Measurement engine with up to quad-band to support precise positioning algorithms
- Code phase, carrier phase, and Doppler frequency measurement
- Supports any SBAS systems
- Independent GPS/QZSS L5, Galileo E5a/b, and BeiDou B2a acquisition and tracking
- 192 (96 data and 96 pilot) signal-tracking channels
Measurement engine core
- Arm Cortex-M7
- Embedded RAM/NVM/cache
Positioning engine core (RTK/PPP)
- Arm Cortex-M7
- Positioning engine core to support decimeter-level positioning firmware (RTK/PPP clients)
- Open platform (SDK offer) for precise positioning software partners
- Operating frequency up to 314MHz
- Double-precision floating-point unit
- Embedded cache (16KB + 16KB)
- Embedded 512KB RAM
External octo-SPI memory interface
- Quad/octal flash/RAM controller
- HyperBus™ flash/RAM controller

Security
- Cybersecurity (ISO 21434) support (STA8610AS1 only)
- Chip integrity (secure boot, secure firmware update, secure link) thanks to embedded hardware security module (HSM) (STA8610AS1 only)
- Signal integrity (antijamming/antispoofing)
- Interface integrity (on-the-fly decryptor engine) (STA8610AS1 only)
Communication interfaces
- 3x UART ports for host communication supporting hardware flow control
- 2x synchronous serial ports (SSP) for host communication or STA5635A RFIC programming
- I²C port for sensor interfacing
- SPIQ port for sensor interfacing
- 2x PPS configurable outputs
- IQ interface to support dual antenna architecture (with external STA5635x)
- 2x timestamp inputs (PPS_IN)
Core peripherals
- Embedded DMA
- 32kHz oscillator real-time clock
- Watchdog timer
- Nested vector interrupt controller
- JTAG
Power management unit
- Separate power supply domains
  - 1.71V to 3.63V backup domain
  - 1.71V to 3.63V switchable domain
  - 0.9V to 1V optional external core supply voltage
- On-chip LDOs with high-voltage/low-voltage monitors
LFBGA100 package with 0.8mm ball pitch
8.5mm x 8.5mm x 1.4mm dimensions