Texas Instruments DS160UP822 8-Channel Linear Redrivers
Texas Instruments DS160UP822 8-Channel Linear Redrivers are low-power, high-performance linear redriver designed to support Ultra Path Interface (UPI) 2.0 up to 16Gbps. The device is a protocol-agnostic linear redriver that can operate for many differential interfaces. The DS160UP822 receivers deploy continuous-time linear equalizers (CTLE) to provide a high-frequency boost. The equalizer can open an input eye that is completely closed due to inter-symbol interference (ISI) induced by an interconnect medium, such as PCB traces and cables. The linear redriver, along with the passive channel, as a whole, gets link trained for the best transmit and receive equalization settings resulting in the best electrical link and lowest possible latency. Low channel-channel cross-talk, low additive jitter, and excellent return loss allow the device to become almost a passive element in the link. The device has an internal linear voltage regulator to provide a clean power supply for high-speed datapaths that provide high immunity to any supply noise on the board. The Texas Instruments DS160UP822 implements high-speed testing during production for reliable high volume manufacturing. The device also has low AC and DC gain variation, providing consistent equalization in high volume platform deployment.Features
- Eight channel linear equalizer supporting UPI 2.0 up to 16Gbps
- Protocol agnostic linear redriver supporting many high speed interface including DisplayPort, SAS, SATA, XFI
- Provides four 2x2 Crosspoint mux function
- CTLE boosts up to 18dB at 8GHz
- Ultra-low latency of 90ps
- Low additive random jitter of 70fs with PRBS data
- Single 3.3V supply
- Low active power of 107mW/channel
- No heat sink required
- Pin-strap, SMBus / I2C or EEPROM programming
- Seamless support for link training
- Support for x4, x8, x16, x24 bus width with one or multiple DS160UP822
- Industrial temperature range of –40°C to 85°C
- 5.5mm × 10mm, 64-pin WQFN package
Applications
- Rack server
- Microserver & tower server
- High performance computing
- Hardware accelerator
Functional Block Diagram
Publicado: 2021-02-08
| Actualizado: 2022-03-11
