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Renesas Electronics 9ZX21901D Clock Buffers

Renesas Electronics 9ZX21901D Clock Buffers are the second-generation DB1900Z differential buffer for Intel Purley and newer platforms. These clock buffers are backward compatible with the 9ZX21901C clock buffer while offering much-improved phase jitter performance. The 9ZX21901D clock buffers can provide outputs up to 400MHz in bypass mode. These buffers feature fixed feedback paths, spread spectrum compatibility, and an SMBus interface. Typical applications include servers, storage, and networking.

Features

  • Fixed feedback path 0ps with input-to-output delay
  • 9 Selectable SMBus addresses where multiple devices can share the same SMBus segment
  • 8 dedicated OE# pins with hardware control of outputs
    • PLL or bypass mode PLL can de-jitter incoming clock
  • Selectable PLL BW minimizes jitter peaking in downstream PLL's
  • Hardware or software control of PLL operating mode changes mode with software mode and does not need a power cycle
  • Spread spectrum compatible are tracks spreading input clock for EMI reduction
  • SMBus Interface are unused outputs that can be disabled
  • 100MHz and 133.33MHz PLL mode is legacy QPI support
  • 72-QFN 10mm x 10mm package small board footprint
  • PCIe clocking architectures supported:
    • Common Clocked (CC)
    • Separate Reference No Spread (SRNS)
    • Separate Reference Independent Spread (SRIS)
  • Output: 19 HCSL output pairs

Specifications

  • Less than 50ps cycle-to-cycle jitter
  • Less than 50ps output-to-output skew
  • Input-to-output delay fixed at 0ps
  • Less than 50ps input-to-output delay variation
  • Less than 0.5ps rms phase jitter PCIe Gen4
  • Less than 0.1ps rms phase jitter UPI 9.6GB/s

Block Diagram

Block Diagram - Renesas Electronics 9ZX21901D Clock Buffers
Publicado: 2018-07-04 | Actualizado: 2023-01-25