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Renesas Electronics 9ZML12x2E Clock Buffers

Renesas Electronics 9ZML12x2E Clock Buffers are second-generation 2-input/12-output differential MUX for Intel Purley and newer platforms. These clock buffers exceed the demanding DB1200ZL performance specifications and are backward compatible with the 9ZML1232B clock buffer. The 9ZML12x2E buffers utilize low-power, High-speed Current Steering Logic (HCSL) compatible outputs to reduce power consumption and termination resistors. Features include nine selectable SMBus addresses, Phase-Locked-Loop (PLL) or bypass mode, spread spectrum compatibility, and SMBus interface. These clock buffers provide two configurable low-drift I2O settings, one for each input channel, allowing I2O tuning for various topologies. Typical applications include servers, storage, networking, and PCI-Express Gen1–4 or QPI/UPI applications.

Features

  • 2 configurable low drift I2O delays up to 2.9ns maintain
    transport delay for various topologies
  • LP-HCSL outputs eliminate 24 resistors (9ZML1232E)
  • LP-HCSL outputs with Zout = 85Ω eliminate 48 resistors
    (9ZML1252E)
  • 9 selectable SMBus addresses where multiple devices can share the same SMBus segment
  • Separate VDDIO for outputs allows maximum power savings
  • PLL or Bypass mode can de-jitter incoming clock
  • PCIe clocking architectures support
    • Common Clocked (CC)
    • Separate Reference No Spread (SRNS)
    • Separate Reference Independent Spread (SRIS)
  • Hardware or software-selectable PLL BW minimizes jitter
    peaking in downstream PLLs
  • Spread spectrum compatible tracks spreading input clock for
    EMI reduction
  • SMBus interface software can modify device settings without
    hardware changes
  • 10mm x 10mm 72-QFN package small board footprint
  • Output features
    • 12 Low-power HCSL (LP-HCSL) output pairs (9ZML1232E)
    • 12 Low-power HCSL (LP-HCSL) output pairs with 85Ω
      Zout (9ZML1252E)

Specifications

  • Cycle-to-cycle jitter < 50ps
  • Output-to-output skew < 50ps
  • Input-to-output delay fixed at 0ps
  • Input-to-output delay variation < 50ps
  • Phase jitter PCIe Gen4 < 0.5ps rms
  • Phase jitter UPI > 9.6GB/s < 0.1ps rms

Applications

  • Servers
  • Storage
  • Networking
  • Solid State Drives (SSDs)

Block Diagram

Block Diagram - Renesas Electronics 9ZML12x2E Clock Buffers
View Results ( 4 ) Page
Número de referencia Hoja de datos Descripción Corriente de suministro operativa
9ZML1252EKILF 9ZML1252EKILF Hoja de datos Tampón de señales de reloj 9ZML1252E DB1200ZL MUX DERIV LITE 22 mA
9ZML1232EKILF 9ZML1232EKILF Hoja de datos Tampón de señales de reloj 9ZML1232E DB1200ZL MUX DERIV 13 mA
9ZML1232EKILFT 9ZML1232EKILFT Hoja de datos Tampón de señales de reloj 9ZML1232E DB1200ZL MUX DERIV 13 mA
9ZML1252EKILFT 9ZML1252EKILFT Hoja de datos Tampón de señales de reloj 9ZML1252E DB1200ZL MUX DERIV LITE 22 mA
Publicado: 2018-05-28 | Actualizado: 2023-01-23