onsemi / Fairchild TinyLogic® UHS Series
onsemi / Fairchild TinyLogic UHS Series are single and dual gate logic devices with ultra-high speed and high drive performance of LCX. The TinyLogic UHS Series operates in a VCC voltage range of 1.65V to 5.5V, and has input overvoltage tolerance, enabling them to interface with 5V components while operating at 3V. The TinyLogic UHS Series gives design engineers the ability to implement design changes without having to redesign complex silicon subcomponents or printed circuit board layouts. The onsemi / Fairchild TinyLogic UHS Series is primarily intended for use in space-constrained systems such as portable CD players, disk drives, cellular phones, pagers, radios, PCMCIA cards, and portable computers.Features
- 1.65V to 5.5V VCC Supply Operation
- Power-Off High-Impedance Inputs and Outputs
- Over-Voltage Tolerance Inputs Facilitate 5V to 3V Translation
- Quite Series™ Noise/EMI Reduction Circuitry
- Ultra Small MicroPak™ Packages
View Results ( 24 ) Page
| Número de referencia | Hoja de datos | Descripción | Tiempo de retraso de propagación |
|---|---|---|---|
| NL17SZ157DFT2G | ![]() |
Codificadores, Decodificadores, Multiplexores y Demultiplexores TinyLogic UHS 2-Input Non-Inverting Multiplexer | 6 ns |
| NC7SZ157FHX | ![]() |
Codificadores, Decodificadores, Multiplexores y Demultiplexores TinyLogic UHS 2Input Non-Invrt Multiplex | |
| NC7SZ57FHX | ![]() |
Puertas lógicas TinyLogic UHS Uni Cnfg 2-In Logic Gate | 3.4 ns |
| NC7SZ19L6X | ![]() |
Codificadores, Decodificadores, Multiplexores y Demultiplexores 1-of-2 Dec/Demult | |
| NC7SZU04FHX | ![]() |
Inversores TinyLogic UHS Unbuffered Inverter | |
| NC7WZ14L6X | ![]() |
Inversores Dl Inv Sch Trigger | |
| NC7SZ05M5X | ![]() |
Inversores UHS Inverter | 12.9 ns at 1.65 V, 10.5 ns at 1.8 V, 7 ns at 2.5 V, 5 ns at 3.3 V, 4.3 ns at 5 V |
| NC7SZ38L6X | ![]() |
Puertas lógicas 2-Input NAND Gate | 2.2 ns |
| NC7SZ57L6X | ![]() |
Puertas lógicas 2-Input Logic Gate | 3.4 ns |
| NC7WZ14FHX | ![]() |
Inversores UHS Dual Inverter w/Sch Trig Inputs | 3.2 ns |
Publicado: 2011-12-08
| Actualizado: 2022-03-11

