Intel Concentrador de controladores de memoria (MCH) de conjuntos de chips 3010
El concentrador de controladores de memoria (MCH) de conjuntos de chips 3010 de Intel está diseñado para utilizarse con la secuencia 600 del procesador Pentium 4 de Intel, las secuencias 800 y 900 del procesador Pentium D de Intel , Intel Celeron D y la serie 3000 del procesador Dual-Core Intel Xeon en el paquete LGA775 en las plataformas de servidor de nivel de entrada UP. El conjunto de chips contiene dos componentes: concentrador de controladores de memoria (MCH) y concentrador de controladores de E/S de Intel 7 (ICH7). El MCH se interconecta con el procesador, la memoria principal, PCI Express y el ICH7. El ICH7 es el concentrador de controladores de E/S de séptima generación y ofrece varias funciones relativas a la E/S.
Features
- Supports a single Intel Pentium 4, Intel Pentium D, Intel Celeron D, and Dual-Core Intel® Xeon® Processor
- Supports Pentium 4 processor FSB interrupt delivery
- 533/800/1066 MT/s (133/200/266 MHz core) FSB
- Supports Hyper-Threading Technology (HT Technology)
- FSB Dynamic Bus Inversion (DBI)
- 36-bit host addressing for access to 8 GB of memory space
- 12-deep In-Order Queue
- 1-deep Defer Queue>
- GTL+ bus driver with integrated GTL termination resistors
- Supports a Cache Line Size of 64 bytes
- A chip-to-chip connection interface to Intel ICH7
- 2 GB/s point-to-point DMI to ICH7 (1 GB/s each direction)
- 100 MHz reference clock (shared with PCI Express Interface)
- 32-bit downstream addressing
- Messages and Error Handling
- PCI Express Interface Support: two PCI Express ports (two x8/x4/x1, or one x16)
- Peer-to-peer Writes
- Compatible with the PCI Express Base
- Raw bit rate on data pins of 2.5 Gb/s resulting in a real bandwidth per pair of 250 MB/s
- Maximum theoretical aggregate bandwidth of 8 GB/s when x16
- 8 GB maximum memory
- Up to two 64-bit wide DDR2 SDRAM channels
- DDR2 memory DIMM frequencies of 533 MHz and 667 MHz
- Asymmetric or Interleaved modes
- Bandwidth up to 10.7 GB/s (DDR2 667) in dual- channel Interleaved mode
- ECC (Error Correcting Code) memory
- 256 Mb, 512 Mb and 1 Gb DDR2 technologies
- Four banks for DDR2 devices up to 512 Mb density; eight banks for 1 Gb DDR2 devices
- Unbuffered DIMMs only
- Page sizes of 4 KB, 8 KB, and 16 KB
- Opportunistic refresh
- Up to 64 simultaneously open pages
- SPD (Serial Presence Detect) scheme for DIMM detection support
- Supports configurations defined in the JEDEC DDR2 DIMM specification only
Specifications
- Memory Specifications
- 8GB Max Memory Size (dependent on memory type)
- DDR2-533/DDR2-667 Memory Types
- 2 Memory Channels
- 10.7 GB/s Max Memory Bandwidth
- 36-bit Physical Address Extensions
- ECC Memory Supported
- Expansion Options
- PCI Express Revision 1.1
- 2x8/x4/x1 or 1x16 PCI Express Configurations
- Package Specifications
- 1 Max CPU Configuration
- 105ºC TCASE
- 34.0mm x 34.0mm package size
- Low Halogen Options Available: See MDD
